Photodiode gate dielectric protection layer

ABSTRACT

The present disclosure relates to a method the present disclosure relates to an integrated chip having an active pixel sensor with a gate dielectric protection layer that reduces damage to an underlying gate dielectric layer during fabrication, and an associated method of formation. In some embodiments, the integrated chip has a photodetector disposed within a substrate, and a gate structure located over the substrate. A gate dielectric protection layer is disposed over the substrate and extends from along a sidewall of the gate structure to a location overlying the photodetector. The gate dielectric protection layer has an upper surface that is vertically below an upper surface of the gate structure.

REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. application Ser. No. 14/867,070 filed on Sep. 28, 2015, which is a continuation of U.S. application Ser. No. 13/948,217, filed on Jul. 23, 2013 (now U.S. Pat. No. 9,147,710, issued on Sep. 29, 2015). This application hereby incorporates by reference all subject matter of the U.S. Applications.

BACKGROUND

Photodiodes are widely used in many modern day electronic devices to convert light into an electric signal (e.g., a voltage or a current). A photodiode is a p-n junction (i.e., an interface between a p-type region and an n-type region) or PIN structure within a semiconductor substrate. Photodiodes are typically formed within an exposed surface of a semiconductor substrate to allow the photodiode to receive light.

During operation, when a photon of sufficient energy strikes a photodiode it excites an electron within a semiconductor substrate of the photodiode, thereby generating an electron-hole pair. As electrons and holes are generated, the holes move in the semiconductor substrate in an opposite direction as the electrons to generate a current.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A-1B illustrate cross-sectional views of some embodiments of a active pixel sensor comprising a gate dielectric protection layer.

FIG. 2 illustrates a flow chart of some embodiments of a method of forming an active pixel sensor comprising a gate dielectric protection layer.

FIGS. 3-12 illustrate some embodiments of a semiconductor substrate upon which method of forming an active pixel sensor is enacted, according to the method of FIG. 2.

DETAILED DESCRIPTION

The description herein is made with reference to the drawings, wherein like reference numerals are generally utilized to refer to like elements throughout, and wherein the various structures are not necessarily drawn to scale. In the following description, for purposes of explanation, numerous specific details are set forth in order to facilitate understanding. It will be appreciated that the details of the figures are not intended to limit the disclosure, but rather are non-limiting embodiments. For example, it may be evident, however, to one of ordinary skill in the art, that one or more aspects described herein may be practiced with a lesser degree of these specific details. In other instances, known structures and devices are shown in block diagram form to facilitate understanding.

Active pixel sensors comprise a semiconductor substrate having a photodetector connected to multiple transistor devices. During fabrication of the transistor devices the semiconductor substrate undergoes numerous etching processes. The etching processes can damage the gate dielectric material of the transistor devices and the underlying semiconductor substrate. For example, during fabrication of a gate structure, polysilicon may be selectively etched using a dry etching process that can cause a loss of gate dielectric material and/or that can damage the underlying semiconductor substrate. Similar damage to the gate dielectric material and/or underlying semiconductor substrate can occur during hard mask removal, sidewall spacer etching, and photoresist ashing process, for example.

The removal of gate dielectric material results in a thinner gate dielectric material outside of the transistor device, adversely affecting the number white pixels and/or the dark current of the active pixel sensor. For example, overetching during the formation of sidewall spacers can cause the number white pixels of an active pixel sensor to decrease. To prevent such an adversely effect in white pixels and/or the dark current of the active pixel sensor, a thicker gate dielectric material can be used, however the thicker gate dielectric material will increase the read noise, the random telegraph signal, and/or the power consumption of the active pixel sensor.

Accordingly, the present disclosure relates to an active pixel sensor having a gate dielectric protection layer configured to reduce damage to an underlying gate dielectric layer and/or semiconductor substrate during fabrication, and an associated method of formation. In some embodiments, the active pixel sensor comprises a photodetector disposed within a semiconductor substrate. A transfer transistor comprising a first gate structure is located on a first gate dielectric layer disposed above the semiconductor substrate. A reset transistor comprising a second gate structure is located on the first gate dielectric layer. A gate dielectric protection layer is disposed onto the gate dielectric at a position extending between the first gate structure and the second gate structure and over the photodetector. The gate dielectric protection layer is configured to protect the gate dielectric from etching procedures during fabrication of the active pixel sensor.

FIGS. 1A-1B illustrate cross-sectional views corresponding to some embodiments of an active pixel sensor 100 comprising a gate dielectric protection layer 118.

As shown in FIG. 1A, the active pixel sensor (APS) 100 comprises a photodetector 107 disposed within a semiconductor substrate 102. In some embodiments, the photodetector 107 may comprise a pinned photodiode. The photodetector 107 has a first doped region 108 and a second doped region 110 disposed within the semiconductor substrate 102. In some embodiments, the first doped region 108 may have a first doping type (e.g., a p-type doping), the second doped region 110 may have a second doping type different than the first doping type (e.g., an n-type doping), and the semiconductor substrate 102 may have the first doping type (e.g., the p-type doping).

Isolation regions 104 are disposed along a perimeter of the APS 100 to provide isolation of the APS 100 from adjacent active pixel sensors. In some embodiments, the isolation regions 104 may comprise shallow trench isolation regions. In additional embodiments, an isolation implantation 106 may be disposed around the isolation regions 104. A gate dielectric layer 116 is disposed over the semiconductor substrate 102 at a position between the isolation regions 104. In some embodiments, the gate dielectric layer 116 may comprise a silicon dioxide (SiO₂) layer. The gate dielectric layer 116 may have a thickness that is less than or equal to approximately 50 angstroms.

A first gate structure 122 a and a second gate structure 122 b are disposed over the gate dielectric layer 116. The first gate structure 122 a comprises a stack having a gate material 124 a and a silicide layer 126 a flanked by a first sidewall spacer 128 a. The second gate structure 122 b comprises a stack having a gate material 124 b and a silicide layer 126 b flanked by a second sidewall spacer 128 b. In some embodiments, the sidewall spacers, 128 a and 128 b, may comprise nitride spacers. The first gate structure 122 a is comprised within a transfer transistor 125 a. The second gate structure 122 b is comprised within a reset transistor 125 b. Gate contacts 130 a and 130 b, configured to connect the transfer transistor 125 a and the reset transistor 125 b to one or more metal interconnect layers, are located above silicide layers 126 a and 126 b, respectively.

During operation, photons striking the surface of the photodetector 107 generate electrons which are collected in the first doped region 108. When the transfer transistor 125 a is turned on, the photon-generated electrons in the first doped region 108 are transferred to the floating diffusion region 112 as a result of a potential difference existing between the photodetector 107 and floating diffusion region 112 (which is further connected to the gate of a read-out transistor that is not shown). The charges are converted to voltage signals by a source follower transistor (not shown). Prior to charge transfer, the floating diffusion region 112 is set to a predetermined low charge state by turning on the reset transistor 125 b, which causes electrons in the floating diffusion region 112 to flow into a voltage source connected to a source/drain region 114.

A gate dielectric protection layer 118 is disposed over the semiconductor substrate 102 at a position that overlies the gate dielectric layer 116. The gate dielectric protection layer 118 extends between the first gate structure 122 a and the second gate structure 122 b without overlying a top of the first gate structure 122 a or the second gate structure 122 b. In some embodiments, the gate dielectric protection layer 118 extends from a first position between a first sidewall spacer 128 a flanking the first gate structure 122 a and the first gate dielectric layer 116 a to a second position between a second sidewall spacer 128 b flanking the second gate structure 122 b and the first gate dielectric layer 116 a. The gate dielectric protection layer 118 also extends to a position that overlies the photodetector 107. In some embodiments, the gate dielectric protection layer 118 is further disposed below a contact etch stop layer (CESL) 120.

In some embodiments, the gate dielectric protection layer 118 is disposed as a conformal thin film that abuts the isolation regions 104, the gate dielectric layer 116, and the gate material 124. In some embodiments, the gate dielectric protection layer 118 may extend along at least a lower portion of sidewalls of the gate material 124. In various embodiments, the gate dielectric protection layer 118 may comprise an oxide layer (e.g., SiO₂), a silicon nitride layer (SiN), or a high-k dielectric material (e.g., hafnium oxide (HfO2), aluminum oxide (Al₂O₃), titanium oxide (TiO₂), HfZrO, Ta₂O₃, HfSiO₄, ZrO₂, ZrSiO₂, etc).

The gate dielectric layer 116 provides for a dielectric material (i.e., a gate dielectric layer 116 and a gate dielectric protection layer 118) having a low thickness (e.g., less than 50 angstroms) below the gate structure 112 a and for a thicker dielectric material outside of the gate structure 112 a. The low thickness of dielectric material provides for good power consumption, read noise, and radio telegraph signals for the APS 100. The thicker dielectric provides for good dark current and white pixel number.

As shown in FIG. 1B, the gate dielectric protection layer 118 has a first thickness t₁ at a location that is under the sidewall spacers 128 of the transistor devices, 125 a and 125 b, and a second thickness t₂ at a location that is outside of the sidewall spacers 128 of the transistor devices, 125 a and 125 b. In some embodiments, the first thickness t₁ may have a range of between approximately 50 angstroms and approximately 250 angstroms. The difference between the first thickness t₁ and the second thickness t₂ (i.e., t₁−t₂) may be in a range of between approximately 10 angstroms and approximately 200 angstroms.

FIG. 2 illustrates a flow chart of some embodiments of a method 200 of forming an active pixel sensor comprising a photodiode gate dielectric protection layer.

While method 200 is illustrated and described below as a series of acts or events, it will be appreciated that the illustrated ordering of such acts or events are not to be interpreted in a limiting sense. For example, some acts may occur in different orders and/or concurrently with other acts or events apart from those illustrated and/or described herein. In addition, not all illustrated acts may be required to implement one or more aspects or embodiments of the description herein. Further, one or more of the acts depicted herein may be carried out in one or more separate acts and/or phases.

At 202, a semiconductor substrate having a doped region is provided. The semiconductor may comprise a first doping type (e.g., the p-type doping), while the doped region may comprise a second doping type (e.g., an n-type doping) different than the first doping type.

At 204, a gate dielectric layer is formed over the semiconductor substrate.

At 206, a gate material is formed over the gate dielectric layer.

At 208, a hard mask layer is selectively formed over the gate material. In various embodiments, the hard mask layer may comprise a silicon nitride layer or a silicon dioxide layer.

At 210, a first etching process is performed to selectively etch the gate material according to the hard mask layer. The first etching process results in a first region of gate material corresponding to a transfer transistor and a second region of gate material corresponding to a reset transistor.

At 212, a conformal dielectric layer is formed over the semiconductor substrate. The conformal dielectric layer overlies the gate dielectric layer, the first and second regions of gate material, and the hard mask layer.

At 214, a second etching process is performed to selectively etch the conformal dielectric layer. In some embodiments the second etching process may be performed to selectively etch the conformal dielectric layer according to a first photoresist layer. The first photoresist layer may be formed to cover a portion of the conformal dielectric layer. For example, the first photoresist layer may expose the conformal dielectric layer at positions corresponding to a top of the gate material. The second etching process generates a gate dielectric protection layer comprising a remainder of the conformal dielectric layer. In some embodiments, the gate dielectric protection layer overlies the gate dielectric layer and sidewalls of the gate material, but does not overlay a top of the gate material.

At 216, a third etching process is performed to remove the hard mask layer. The third etching process may reduce the thickness of the gate dielectric protection layer. It will be appreciated that since the third etching process exposes both the hard mask layer and the gate dielectric protection layer, that a material of the hard mask layer may be selected based upon a material of the gate dielectric protection layer. For example, if the gate dielectric protection layer comprises a SiO₂ layer, the hard mask layer may be selected to comprise a SiON material, while if the gate dielectric protection layer comprises a SiN layer, the hard mask layer may be selected to comprise a SiO₂ material.

At 218, sidewall spacers are formed flanking sides of the gate material.

At 220, a pinned photodiode implantation is performed to form a pinned photodiode within the semiconductor substrate.

At 222, a source and drain implantation is selectively performed to form source and drain regions of the transfer transistor and the reset transistor. In some embodiments, the source and drain implantation is performed according to a second photoresist layer.

At 224, the second photoresist layer may be removed by a source/drain ashing process. Removal of the second photoresist layer reduces the thickness of the gate dielectric protection layer to have a greater thickness underneath sidewall spacers of the transfer transistor and the reset transistor than outside of the sidewall spacers of the transfer transistor and the reset transistor.

At 226, one or more metal interconnect layers are formed above the transfer transistor and the reset transistor.

FIGS. 3-12 illustrate some embodiments of an exemplary semiconductor substrate, whereon a method of etching according to method 200 is implemented. Although FIGS. 3-12 are described in relation to method 200, it will be appreciated that the structures disclosed in FIGS. 3-12 are not limited to such a method.

FIG. 3 illustrates some embodiments of a cross-sectional view 300 of a substrate corresponding to acts 202-204.

The substrate comprises a semiconductor substrate 102 and an overlying gate dielectric layer 116. The semiconductor substrate 102 may comprise any type of semiconductor body (e.g., silicon, silicon-germanium, silicon-on-insulator) such as a semiconductor wafer and/or one or more die on a wafer, as well as any other type of semiconductor and/or epitaxial layers associated therewith. In some embodiments, the semiconductor substrate 102 comprises a first doping type (e.g., a p-type doping).

The gate dielectric layer 116 is formed over the semiconductor substrate 102 between first and second isolation regions, 104 a and 104 b, located along outer edges of an active pixel sensor region 302 comprising a first doped region 108 having a second doping type (e.g., an n-type doping). The first gate dielectric has a thickness that is less than or equal to approximately 50 angstroms.

In some embodiments, the semiconductor substrate 102 may further comprise a periphery region 304 (i.e., an I/O region) spatially separated on an integrated chip from the active pixel sensor region 302. The periphery region 304 comprises one or more well regions 306 having the second doping type. The one or more well regions 306 are separated from one another by isolation regions 104 c-104 e (e.g., shall trench isolation regions). In some embodiments, the gate dielectric layer 116 may be deposited through a dual gate dielectric process, in which the gate dielectric layer 116 is formed to have a first gate dielectric layer 116 a having a first thickness and a second gate dielectric layer 116 b having a second thickness, different than the first thickness. The first gate dielectric layer 116 a is disposed over the first doped region 108, the semiconductor substrate of the active pixel sensor region 302, and a well region of the periphery region 304 associated with 110 transistor devices. The second gate dielectric layer 116 b is disposed over a well region of the periphery region 304 associated with core transistor devices.

FIG. 4 illustrates some embodiments of a cross-sectional view 400 of a substrate corresponding to acts 206-210.

As shown in cross-sectional view 400, a gate material 124 is selectively formed above the gate dielectric layer 116. The gate material 124 may be formed onto the semiconductor substrate 102 by way of a deposition technique (e.g., chemical vapor deposition, physical vapor deposition, etc.). In some embodiments, the gate material 124 may comprise polysilicon. In other embodiments, the gate material 124 may comprise a high-k metal gate material (e.g., aluminum, aluminum oxide, etc.).

In some embodiments, the gate material 124 may be deposited as a blanket deposition over the surface of the semiconductor substrate 102 and a hard mask layer 402 may be selectively formed over the gate material 124 to define gate structures. A first etching process is then performed to selectively etch the gate material 124 according to the hard mask layer 402. In some embodiments, the hard mask layer 402 may comprise silicon oxy-nitride (SiON) or silicon dioxide (SiO₂).

FIG. 5 illustrates some embodiments of a cross-sectional view 500 of a substrate corresponding to act 212.

As shown in cross-sectional view 500, a conformal dielectric layer 502 is formed onto the substrate. In some embodiments, the conformal dielectric layer 502 is formed to a thickness having a range of between approximately 30 angstroms and approximately 50 angstroms. In various embodiments, the conformal dielectric layer 502 may be formed using a thermal process or a deposition process (e.g., physical layer deposition, chemical vapor deposition, atomic layer deposition, etc.).

The conformal dielectric layer 502 is formed onto the semiconductor substrate at a position over the gate dielectric layer 116. In some embodiments, the conformal dielectric layer 502 is formed as a thin film that abuts isolation regions 104 a-104 b, the gate dielectric layer 116, the gate material 124, and the hard mask layer 402. In various embodiments, the conformal dielectric layer 502 may comprise an oxide layer, a silicon nitride layer, or a high-k dielectric material (e.g., hafnium oxide (HfO₂), aluminum oxide (Al₂O₃), titanium oxide (TiO₂), HfZrO, Ta₂O₃, HfSiO₄, ZrO₂, ZrSiO₂, etc).

In some embodiments, the hard mask layer 402 is selected to comprise a material based upon a material of the conformal dielectric layer 502. For example, if the conformal dielectric layer 502 comprises an oxide layer, the hard mask layer 402 may be selected to comprise a SiON material. If the conformal dielectric layer 502 comprises a SiN layer, the hard mask layer 402 may be selected to comprise a SiO₂ material. If the conformal dielectric layer 502 comprises a high-k dielectric material, the hard mask layer 402 may be selected to comprise a SiON material.

FIGS. 6-7 illustrate some embodiments of cross-sectional views, 600 and 700, of a substrate corresponding to act 214.

As shown in cross-sectional view 600, a first photoresist layer 602 is selectively formed over the semiconductor substrate 102. The first photoresist layer 602 is formed at a position that exposes a top portion of the gate material 124 and hard mask layer 402. In some embodiments, the first photoresist layer 602 may be formed by spinning photoresist onto the semiconductor substrate 102 as the semiconductor substrate 102 is rotated at a high rate of RPMs. The first photoresist layer 602 may subsequently be selectively exposed to form soluable sections overlying the gate material 124. The first photoresist layer 602 may then be developed, using a chemical developer to remove soluable sections from the semiconductor substrate 102.

As shown in cross-sectional view 700, a second etching process is performed by selectively exposing the semiconductor substrate 102 to an etchant 702 (e.g., a wet etchant or a dry etchant) that removes the conformal dielectric layer 502 from a top portion of the gate material 124 and the hard mask layer 402 to generate a gate dielectric protection layer 118 that overlies the gate dielectric layer 116. The gate dielectric protection layer 118 is configured to protect the underlying gate dielectric layer 116 from subsequent etching processes. By protecting the gate dielectric layer 116 from subsequent etching processes the gate dielectric layer 116 can have a low thickness (e.g., less than 50 angstroms) below the gate material to provide for good power consumption, read noise, and radio telegraph signals of the APS, while providing for a thick dielectric outside of the gate material that provides for good dark current and white pixel number.

In some embodiments, after the second etching process is completed the gate dielectric protection layer 118 may extend along at least a lower portion of the gate material 124. For example, the gate dielectric protection layer 118 may be removed from the hard mask layer 402 and a portion of the underlying gate material 124.

FIG. 8 illustrates some embodiments of a cross-sectional view 800 of a substrate corresponding to act 216.

As shown in cross-sectional view 800, the hard mask layer 402 is removed from the semiconductor substrate 102. The hard mask layer 402 is removed by exposing the semiconductor substrate 102 to an etchant 802 that removes the hard mask layer 402. The etchant 802 also acts upon the gate dielectric protection layer 118, thereby consuming some of the gate dielectric protection layer 118.

FIG. 9 illustrates some embodiments of a cross-sectional view 900 of a substrate corresponding to acts 218-220.

As shown in cross-sectional view 900, a silicide layer 126 is formed onto the gate material 124. The silicide layer 126 may comprise a silicon-nitride (SiN) material. Sidewall spacers 128 are then formed to flank sides of the gate material 124 and the silicide layer 126. In some embodiments, the sidewall spacers 128 may be formed by depositing nitride onto the semiconductor substrate 102 and selectively etching the nitride to form the sidewall spacers 128. In some embodiments, a dielectric material 902, such as an oxide, may be positioned between the sidewall spacers 128 and the gate dielectric protection layer 118.

A photodiode implantation 904 is performed by implanting a dopant into the semiconductor substrate 102 in the first doped region 108 to form a photodetector 107 (e.g., a pinned photodiode). The photodiode implantation 904 forms a second doped region 110 within the first doped region 108 of the active pixel sensor region 302. The second doped region 110 may comprise a first doping type (e.g., a p-type doping) that is different than the second doping type of the first doped region 108. For example, in some embodiments, the photodiode implantation 904 may comprise a boron implantation.

FIG. 10 illustrates some embodiments of a cross-sectional view 1000 of a substrate corresponding to act 222.

As shown in cross-sectional view 1000, a second photoresist layer 1002 is selectively formed over the semiconductor substrate 102. The second photoresist layer 1002 comprises an opening that exposes the location of source and drain regions within the semiconductor substrate 102.

A source and drain implantation 1004 is performed to form the source and drain regions of semiconductor devices within the semiconductor substrate 102 according to the second photoresist layer 1002. The source and drain implantation 1004 forms a floating diffusion region 112 and a source/drain region 114 having a second doping type within the active pixel sensor region 302. The source and drain implantation 1004 may also forms source/drain regions 1006 within the periphery region 304.

The source and drain implantation 1004 results in the formation of a transfer transistor 125 a and a reset transistor 125 b within the active pixel sensor region 302. The source and drain implantation 1004 also results in the formation of a core transistor device 1008 and an I/O transistor 1010 within the periphery region. The transfer transistor 125 a, the reset transistor 125 b, and the I/O transistor 1010 have the first gate dielectric layer 116 a comprising the first dielectric thickness, while the core transistor device 1008 has the second gate dielectric layer 116 b comprising the second dielectric thickness.

FIG. 11 illustrates some embodiments of a cross-sectional view 1100 of a substrate corresponding to act 224.

As shown in cross-sectional view 1100, after the source and drain implantation 1004 is completed, the second photoresist layer 1002 is removed from the semiconductor substrate 102 using a source/drain ashing process. In some embodiments, the source/drain ashing process may comprise a dry etching process (e.g., using a CF₄ dry etch chemistry). The ashing process will remove the photoresist but in the process may also remove a portion of the gate dielectric protection layer 118, resulting in a gate dielectric protection layer 118 that has a first thickness t₁ underneath the sidewall spacers 128 of the transistor devices and a second thickness t₂ outside of the sidewall spacers 128 of the transistor devices. In some embodiments, the first thickness t₁ may have a range of between approximately 50 angstroms and approximately 250 angstroms, and the second thickness t₂ may have a range of between approximately 10 angstroms and approximately 200 angstroms.

FIG. 12 illustrates some embodiments of a cross-sectional view 1200 of a substrate corresponding to act 226.

As shown in cross-sectional view 1200, one or more metal interconnect layers 1204 are formed above the transistor devices, 125 a and 125 b. The one or more metal interconnect layers 1204 are disposed within an inter-level dielectric layer 1202 and connected to the transistor devices, 125 a and 125 b, by way of a contact 130. In some embodiments, the inter-level dielectric layer 1202 may comprise a low-k dielectric material (e.g., SiCO) or an ultra low-k dielectric material. In some embodiments, one or more metal interconnect layers 1204 may comprise copper.

It will be appreciated that while reference is made throughout this document to exemplary structures in discussing aspects of methodologies described herein, those methodologies are not to be limited by the corresponding structures presented. Rather, the methodologies and structures are to be considered independent of one another and able to stand alone and be practiced without regard to any of the particular aspects depicted in the Figs.

Also, equivalent alterations and/or modifications may occur to one of ordinary skill in the art based upon a reading and/or understanding of the specification and annexed drawings. The disclosure herein includes all such modifications and alterations and is generally not intended to be limited thereby. For example, although the figures provided herein are illustrated and described to have a particular doping type, it will be appreciated that alternative doping types may be utilized as will be appreciated by one of ordinary skill in the art.

In addition, while a particular feature or aspect may have been disclosed with respect to one of several implementations, such feature or aspect may be combined with one or more other features and/or aspects of other implementations as may be desired. Furthermore, to the extent that the terms “includes”, “having”, “has”, “with”, and/or variants thereof are used herein, such terms are intended to be inclusive in meaning—like “comprising.” Also, “exemplary” is merely meant to mean an example, rather than the best. It is also to be appreciated that features, layers and/or elements depicted herein are illustrated with particular dimensions and/or orientations relative to one another for purposes of simplicity and ease of understanding, and that the actual dimensions and/or orientations may differ from that illustrated herein.

Therefore, the present disclosure relates to an active pixel sensor having a gate dielectric protection layer configured to reduce damage to an underlying gate dielectric layer and/or semiconductor substrate during fabrication, and an associated method of formation.

In some embodiments, the present disclosure relates to an integrated chip. The integrated chip comprises a photodetector disposed within a substrate, and a gate structure located over the substrate. A gate dielectric protection layer is disposed over the substrate and extends from along a sidewall of the gate structure to a location overlying the photodetector. The gate dielectric protection layer has an upper surface that is vertically below an upper surface of the gate structure.

In other embodiments, the present disclosure relates to an integrated chip. The integrated chip comprises a gate structure disposed over a substrate, and a gate dielectric protection layer disposed over the substrate along a sidewall of the gate structure. A sidewall spacer arranged over the gate dielectric protection layer and surrounding the gate structure. The gate dielectric protection layer has a first thickness below the sidewall spacer and a second thickness outside of the sidewall spacer.

In other embodiments, the present disclosure relates to an integrated chip. The integrated chip comprises a gate structure disposed over a substrate, and a gate dielectric protection layer disposed over the substrate along a side of the gate structure. A sidewall spacer is arranged over the gate dielectric protection layer on a side of the gate structure. The gate dielectric protection layer extends from below the sidewall spacer to outside of the sidewall spacer. 

What is claimed is:
 1. An integrated chip, comprising: a photodetector disposed within a substrate; a gate structure located over the substrate; a gate dielectric protection layer disposed over the substrate and extending from along a sidewall of the gate structure to a location overlying the photodetector, wherein the gate dielectric protection layer comprises a lateral segment and a vertical segment protruding outward from an upper surface of the lateral segment and extending along the sidewall of the gate structure; and wherein the gate dielectric protection layer has an upper surface that is vertically below an upper surface of the gate structure.
 2. The integrated chip of claim 1, further comprising: a sidewall spacer arranged along a side of the gate structure, wherein the gate dielectric protection layer continuously extends from below the sidewall spacer to the location over the photodetector.
 3. The integrated chip of claim 2, further comprising: a contact etch stop layer disposed over the gate dielectric protection layer.
 4. The integrated chip of claim 3, wherein the contact etch stop layer is arranged over the gate dielectric protection layer and the sidewall spacer.
 5. The integrated chip of claim 4, further comprising: an inter-level dielectric layer disposed over the contact etch stop layer.
 6. The integrated chip of claim 1, wherein the gate dielectric protection layer comprises hafnium oxide, aluminum oxide, titanium oxide, hafnium zirconate, tantalum oxide, hafnium silicate, zirconium oxide, or zirconium silicate.
 7. The integrated chip of claim 1, wherein the gate dielectric protection layer is configured to reduce damage to an underlying layer during fabrication of the integrated chip.
 8. The integrated chip of claim 1, wherein the gate dielectric protection layer is in direct contact with the sidewall of the gate structure.
 9. An integrated chip, comprising: a gate structure disposed over a substrate; a gate dielectric protection layer disposed over the substrate along a sidewall of the gate structure; and a sidewall spacer arranged over the gate dielectric protection layer and surrounding the gate structure, wherein the gate dielectric protection layer has a first thickness below the sidewall spacer and a maximum second thickness outside of the sidewall spacer, wherein the first thickness is larger than the maximum second thickness.
 10. The integrated chip of claim 9, wherein the first thickness is in a first range of between approximately 50 angstroms and approximately 250 angstroms; and wherein the maximum second thickness is in a second range of between approximately 10 angstroms and approximately 200 angstroms.
 11. The integrated chip of claim 9, wherein the gate structure comprises a gate dielectric layer and an overlying gate electrode layer, wherein the first thickness of the gate dielectric protection layer is greater than or equal to a thickness of the gate dielectric layer.
 12. The integrated chip of claim 9, further comprising: a photodetector disposed within the substrate, wherein the gate dielectric protection layer extends from below the sidewall spacer to a location over the photodetector.
 13. The integrated chip of claim 9, further comprising: a dielectric material comprising a stepped surface arranged between the gate dielectric protection layer and the sidewall spacer.
 14. The integrated chip of claim 9, wherein the sidewall spacer has a stepped sidewall facing the gate structure.
 15. The integrated chip of claim 9, further comprising: a contact etch stop layer disposed over the gate dielectric protection layer and the sidewall spacer.
 16. An integrated chip, comprising: a gate structure disposed over a substrate; a gate dielectric protection layer disposed over the substrate along an outermost sidewall of the gate structure; and a sidewall spacer arranged over the gate dielectric protection layer and contacting a side of the gate structure, wherein the gate dielectric protection layer extends from a first end located outside of the outermost sidewall and below the sidewall spacer to a second end outside of the sidewall spacer.
 17. The integrated chip of claim 16, wherein the gate dielectric protection layer extends from between the sidewall spacer and the substrate to between the sidewall spacer and the gate structure.
 18. The integrated chip of claim 16, further comprising: a photodetector disposed within the substrate, wherein the gate dielectric protection layer extends from below the sidewall spacer to a location over the photodetector.
 19. The integrated chip of claim 16, further comprising: a periphery region comprising one or more transistor devices, wherein the gate dielectric protection layer is arranged below sidewall spacers surrounding the one or more transistor devices and has an outermost sidewall aligned with outermost edges of sidewall spacers.
 20. The integrated chip of claim 19, wherein the outermost sidewall of the gate dielectric protection layer arranged below sidewall spacers surrounding the one or more transistor devices laterally contacts a contact etch stop layer. 